MSP430 basic coding/programing part 2 WDT+

WDT is a very useful tool, as I explained before most of us will turn it off or use it as an interval timer. Timer_A has a similar timer function but more robust and more options.
So today we will be going over WDT and timer_A registers, how to setup them up, how you use them is up the you.

WDT is the watch dog timer, used for checking errors/faults, or software states, interval timer, interval interrupt, or what ever other uses you can think of.

So lets start with the basic register WDTCTL
This is the main register that will configure the WDT, bits 15-8 are the password register and 7-0 are for control. you need to set the password register before you can modify bits 7-0.
to do this WDTCTL = WDTPW; // WDTPW = 0x5A00 or 01011010 00000000
This will allow access to the 7-0 bits to configure the WDT. The rest of the registers are used to turn off, setup, change to interval mode, set interupts, change clock sources, and more.
This next set of registers is taken from the slau144e.pdf from the TI website, this book explains how it all works and what the settings mean.

WDTHOLD Bit 7 Watchdog timer+ hold. This bit stops the watchdog timer+. Setting
WDTHOLD = 1 when the WDT+ is not in use conserves power.

  • 0 Watchdog timer+ is not stopped
  • 1 Watchdog timer+ is stopped
  • WDTNMIES Bit 6 Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the
    NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify
    this bit when WDTIE = 0 to avoid triggering an accidental NMI.

  • 0 NMI on rising edge
  • 1 NMI on falling edge
  • WDTNMI Bit 5 Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin.

  • 0 Reset function
  • 1 NMI function
  • WDTTMSEL Bit 4 Watchdog timer+ mode select

  • 0 Watchdog mode
  • 1 Interval timer mode
  • WDTCNTCL Bit 3 Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count
    value to 0000h. WDTCNTCL is automatically reset.

  • 0 No action
  • 1 WDTCNT = 0000h
  • WDTSSEL Bit 2 Watchdog timer+ clock source select

  • 0 SMCLK
  • 1 ACLK
  • WDTISx Bits 1-0
    Watchdog timer+ interval select. These bits select the watchdog timer+
    interval to set the WDTIFG flag and/or generate a PUC.

  • 00 Watchdog clock source /32768
  • 01 Watchdog clock source /8192
  • 10 Watchdog clock source /512
  • 11 Watchdog clock source /64

  • There are also built in Bit masks to make it easier to code. but we are going for more of an in-depth explanation, because any one can post those and pick and choose the best fit for the project, but you really wont know whats going on behind the scenes right?
    But for those that want to use those we will post those on the bottom.

    From the time you start up your MSP chip to power down. the initial WDT setting is to time out after 32768 cycles of the clock before an interrupt is activated and shuts you down into a low power mode, this will keep happening until the WDT settings are configured to your specs.

    Lets start with simple functions
    WDT is turned off
    simple enough?

    what about a simple timer?
    WDTCTL = WDTPW+WDTTMSEL+WDTCNTCL; //word access WDT_MDLY_32 This is the default interval timer with 32ms interval.
    WDTTMSEL turns on the interval timer mode and WDTCNTCL clears the resets the count.

    This will create an endless loop every ~32ms( when the counter reaches 32768). This could be very useful… change the interval you will need to add WDTIS1 or WDTIS0,
    this sets the interval for the WDT+, just remember what clock your sourcing from. For people who want more readable code word access to settings for WDT are as follows for Interval timer.

    taken from the msp430 header files for msplibc

    /* WDT is clocked by fSMCLK (assumed 1MHz) */
    #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
    #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms ” */
    #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms ” */
    #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms ” */
    /* WDT is clocked by fACLK (assumed 32KHz) */
    #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms ” */

    The other mode for WDT is the watch dog mode, this mode will count the clocks and do an interrupt or a reset. when the WDT count reaches the interval it will set the interrupt flag and either run an interrupt routine or cause a PUC. This is great if you need a PUC when your program freezes or times out waiting for data, or anything else that that would prevent the program from continuing.
    to setup the default settings, this is the same settings used when it powers up and is initializing the program
    this sets up a timer, when the timer is reached, a PUC is generated. PUC = Power UP clear, this is pretty much a soft reset. the interval is ~32ms or 32768 cycles.
    I will not go into interrupts at this time, I will be going over them at another point.
    but the word access setting are

    /* WDT is clocked by fSMCLK (assumed 1MHz) */
    #define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
    #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms ” */
    #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms ” */
    #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms ” */
    /* WDT is clocked by fACLK (assumed 32KHz) */
    #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms ” */
    #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms ” */
    #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms ” */
    #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms ” */

    Other use for the WDT+ is to debounce buttons, detect clock failures or faults.
    If you have any more good examples of how to use the WDT+ let me know and i will add them. For more examples check out my 32KHz crystal post has an example of a fail safe for the 32KHz crystal, or check out TIs Code examples for MSP430.

    Timer_A and PWM is hopefully next, but i may go into USI and ADC functions instead.